The need to handle interlocks is common in computing apparatus. There are other solutions. However, as architectures progress the different problems invariably arise. A barrier which arose to achieving super scalar performance with RISC processors, such as those developed originally for the IBM RISC/System 6000 (tm) is that interlocks are serialized so that the traditional super-scalar hardware is underutilized. There is a need to increase utilization of the hardware for a system, especially in the superscalar area where a machine attempts to issue more than one instruction in a given machine cycle or the machine attempts to execute interlocked instructions in a single cycle. The present description of a 3-1 computing apparatus has provided the answer.